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TDA7443D
TONE CONTROL AND SURROUND DIGITALLY CONTROLLED AUDIO PROCESSOR WITH AGC
PRODUCT PREVIEW
s
s s s s s
s
s
INPUT MULTIPLEXER - 5 STEREO INPUTS - SELECTABLE INPUT GAIN FOR OPTIMAL ADAPTATION TO DIFFERENT SOURCES ONE STEREO OUTPUT AGC TREBLE AND BASS CONTROL IN 2.0dB STEPS VOLUME CONTROL IN 1.0dB STEPS TWO SPEAKER ATTENUATORS: - TWO INDEPENDENT SPEAKER CONTROL IN 1.0dB STEPS FOR BALANCE FACILITY - INDEPENDENT MUTE FUNCTION TWO SURROND MODES AVAILABLE - MUSIC PSEUDO STEREO ALL FUNCTION ARE PROGRAMMABLE VIA SERIAL BUS
SO28 ORDERING NUMBER: TDA7443D
DESCRIPTION The TDA7443D is a volume tone (bass and treble) PIN CONNECTION (Top view)
balance (Left/Right) processor for quality audio applications in Hi-Fi systems. Selectable input gain is provided. Control of all the functions is accomplished by serial bus. The AC signal setting is obtained by resistor networks and switches combined with operational amplifiers. Thanks to the used BIPOLAR/CMOS Technology, Low Distortion, Low Noise and DC stepping are obtained.
VS AGC L-IN1 L-IN2 L-IN3 L-IN4 L-IN5 L-MUX L-TREBLE L-BASSI L-BASSO L-OUT SDA SCL
1 2 3 4 5 6 7 8 9 10 11 12 13 14
D01AU1319
28 27 26 25 24 23 22 21 20 19 18 17 16 15
PS1 LP R-IN1 R-IN2 R-IN3 R-IN4 R-IN5 R-MUX R-TREBLE R-BASSI R-BASSO R-OUT CREF GND
July 2002
This is preliminary information on a new product now in development. Details are subject to change without notice.
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50K 27 28 SURROUND
SURROUND ON
R-IN1 26
SURROUND IN SELECT 14 I2C BUS DECODER + LATCHES 13 SCL SDA
LP
PS1
1.2nF 2 AGC CONTROL MUTE 3 SURROUND IN SELECT
100nF
AGC
100nF
L-IN1
50K 4 INPUT SELECT 50K NON SURROUND MUTE 5
0.47F
SURROUND
L-IN2
SURROUND ON
0.47F
SURROUND
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5.6K 5.6nF 100nF R-BASSI R-BASSO 18 19 100nF R-MUX R-TREBLE 20 22 21 50K 23 RB 50K 24 MUTE 17 NON-SURROUND 25 VOLUME TREBLE BASS BALANCE -63dB att. /1dB step input gain: 0 to 14dB /2dB step AGC gain: 0 to 7dB /1dB step VOLUME IN SELECT -63 att. /1dB step R-OUT -14 to +14dB /2dB step -14 to +14dB /2dB step INPUT SELECT 50K 50K MUTE 12 VOLUME TREBLE BASS BALANCE L-OUT 50K 6 input gain: 0 to 14dB /2dB step AGC gain: 0 to 7dB /1dB step VOLUME IN SELECT -63dB att. /1dB step -14 to +14dB /2dB step -14 to +14dB /2dB step RB 50K 7 SUPPLY -63 att. /1dB step 50K VREF 1 VS GND 15 16 CREF 8 L-MUX 9 L-TREBLE 10 L-BASSI 100nF 22F 5.6nF 100nF 5.6K 11 L-BASSO
TDA7443D
0.47F
R-IN5
0.47F
R-IN4
0.47F
R-IN3
BLOCK DIAGRAM & TEST CIRCUIT
0.47F
R-IN2
0.47F
L-IN3
0.47F
L-IN4
0.47F
L-IN5
0.47F
D01AU1328
TDA7443D
ABSOLUTE MAXIMUM RATINGS
Symbol Vs Tamb Tstg Operating Supply Voltage Operating Ambient Temperature Storage Temperature Range Parameter Value 10.5 -10 to 85 -55 to 150 Unit V C C
THERMAL DATA
Symbol Rth j-pin Parameter Thermal Resistance Junction-pins Value 85 Unit C/W
QUICK REFERENCE DATA
Symbol VS VCL THD S/N SC Supply Voltage Max. input signal handling Total Harmonic Distortion V=1Vrms f=1kHz Signal to Noise Ratio VOUT=1Vrms(mode=OFF) Channel Separation f=1kHz Input Gain (2dB step) AGC Gain (1dB step) Volume Control (1dB step) Treble Control (2dB step) Bass Control (2dB step) Balance Control (1dB step) Mute Attenuation 0 0 -63 -14 -14 -63 90 Parameter Min. 5 2 0.01 100 90 14 7 0 +14 +14 0 0.1 Typ. 9 Max. 10 Unit V Vrms % dB dB dB dB dB dB dB dB dB
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TDA7443D
ELECTRICAL CHARACTERISTICS (Refer to the test circuit Tamb=25C, Vs=9V, f=1kHz ,all controls flat, unless otherwise specified)
Symbol SUPPLY VS IS SVR Supply Voltage Supply Current Ripple Rejection 60 5 9 tbd 80 10 V mA dB Parameter Conditions Min. Typ. Max. Unit
INPUT STAGE RIN VCL SIN Gin min Gin max Gin step AGC GAGCmin Minimum AGC Gain GAGCmax Maximum AGC Gain GAGCstep Step Resolution SURROUND RIN RPS0 RPS1 RPS2 RPS3 CRANGE Sstep Input Resistance Phase Shifter:D1=0,D0=0 Phase Shifter:D1=0,D0=1 Phase Shifter:D1=1,D0=0 Phase Shifter:D1=1,D0=1 Effect Control Range Effect Control Step Resolution 35 8.3 10 12.6 26.4 -21 0.5 1 50 11.8 14.1 17.9 37.3 65 15.2 18.3 23.3 48.85 -6 1.5 k k k k k dB dB -1 6 0.5 0 7 1 1 8 1.5 dB dB dB Input Resistance Clipping Level Input Separation Minimum Input Gain Maximum Input Gain Step Resolution THD = 0.3% 35 2 80 -1 13 1.5 50 2.5 100 0 14 2 1 15 2.5 65 k Vrms dB dB dB dB
VOLUME CONTROL AVOLmin AVOLmax AVOLstep EA Minimum Attenuation Maximum Attenuation Step Resolution Attenuation set error AV = 0 to -24 dB AV = -24 to -63 dB VDC DC Steps Adjacent att. steps -1 61 0.5 -1 -2 -3 0 63 1 0 0 0 1 65 1.5 1 2 3 dB dB dB dB dB mV
BASS CONTROL GB Control Range Max. Boost/Cut 12 14 16 dB
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TDA7443D
ELECTRICAL CHARACTERISTICS (continued) (Refer to the test circuit Tamb=25C, Vs=9V, f=1kHz ,all controls flat, unless otherwise specified)
Symbol Bstep RB Parameter Step Resolution Internal Feedback Resistance Conditions Min. 1 33 Typ. 2 44 Max. 3 55 Unit dB k
TREBLE CONTROL GT Tstep RT Control Range Step Resolution Internal Feedback Resistance Max. Boost/Cut 13 1 14 2 25 15 3 dB dB k
BALANCE CONTROL ABALmin ABALmax ABALstep EA Minimum Attenuation Maximum Attenuation Step Resolution Attenuation set error AV = 0 to -24 dB AV = -24 to -63 dB VDC DC Steps Adjacent att. steps -1 -2 -3 -1 61 0 63 1 0 0 0 1 2 3 1 65 dB dB dB dB dB mV
AUDIO OUTPUTS VOCL RL VOUT NO(OFF) Clipping Level Output Load Resistance DC Voltage Level Output Noise (OFF) BW=20Hz to 20kHz; All gains 0dB; Output muted flat BW=20Hz to 20kHz; Mode=Music BW=20Hz to 20kHz; Mode=Pseudo Stereo THD = 0.3% 2 2 4.5 2.5 Vrms k V
5 10 30 30 90
15
V V V V dB dB dB
NO(MUS) NO(PS) AMUTE S/N SC d
Output Noise (Music) Output Noise(Pseudo Stereo) Output Mute Condition Signal to Noise Ratio Channel Separation Left/Right Distortion
All gains 0dB;VO = 1Vrms
100 90
AV = 0; VI = 1Vrms
0.01
0.1
%
BUS INPUT VIL VIH IIN VO Input Low Voltage Input High Voltage Input Current Output Voltage (ACK) VIN = 0.4V IO = 1.6mA 2.5 -5 0.4 5 0.8 1 V V A V
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TDA7443D
I2C BUS INTERFACE Data transmission from microprocessor to the TDA7443D and vice versa takes place through the 2 wires I2C BUS interface, consisting of the two lines SDA and SCL (pull-up resistors to positive supply voltage must be connected). Data Validity As shown in fig. 1, the data on the SDA line must be stable during the high period of the clock. The HIGH and LOW state of the data line can only change when the clock signal on the SCL line is LOW. Start and Stop Conditions As shown in fig. 2 a start condition is a HIGH to LOW transition of the SDA line while SCL is HIGH. The stop condition is a LOW to HIGH transition of the SDA line while SCL is HIGH. Byte Format Every byte transferred on the SDA line must contain 8 bits. Each byte must be followed by an acknowledge bit. The MSB is transferred first. Acknowledge The master (P) puts a resistive HIGH level on the SDA line during the acknowledge clock pulse (see fig. 3). The peripheral (audio processor) that acknowledges has to pull-down (LOW) the SDA line during this clock pulse. The audio processor which has been addressed has to generate an acknowledge after the reception of each byte, otherwise the SDA line remains at the HIGH level during the ninth clock pulse time. In this case the master transmitter can generate the STOP information in order to abort the transfer. Transmission without Acknowledge Avoiding to detect the acknowledge of the audio processor, the P can use a simpler transmission: simply it waits one clock without checking the slave acknowledging, and sends the new data. This approach of course is less protected from misworking. Figure 1. Data Validity on the I2CBUS
SDA
SCL DATA LINE STABLE, DATA VALID CHANGE DATA ALLOWED
D99AU1031
Figure 2. Timing Diagram of I2CBUS
SCL I2CBUS SDA
D99AU1032
START
STOP
Figure 3. Acknowledge on the I2CBUS
SCL 1 2 3 7 8 9
SDA MSB START
D99AU1033
ACKNOWLEDGMENT FROM RECEIVER
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TDA7443D
SOFTWARE SPECIFICATION Interface Protocol The interface protocol comprises: s A start condition (S)
s s s s
A chip address byte, containing the TDA7440D address A subaddress bytes A sequence of data (N byte + acknowledge) A stop condition (P)
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X B DATA SUBADDRESS LSB ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU420
ACK = Acknowledge;
S = Start;
P = Stop;
A = Address;
B = Auto Increment
EXAMPLES No Incremental Bus The TDA7443D receives a start condition, the correct chip address, a subaddress with the B = 0 (no incremental bus), N-data (all these data concern the subaddress selected), a stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 0 D3 D2 D1 D0 ACK MSB DATA DATA LSB ACK P
D96AU421
Incremental Bus The TDA7443D receivea start conditions, the correct chip address, a subaddress with the B = 1 (incremental bus): now it is in a loop condition with an autoincrease of the subaddress whereas SUBADDRESS from "XXX1000" to "XXX1111" of DATA are ignored.The DATA 1 concern the subaddress sent, and the DATA 2 concern the subaddress sent plus one in the loop etc, and at the end it receivers the stop condition.
CHIP ADDRESS MSB S 1 0 0 0 1 0 0 LSB 0 ACK MSB X X X SUBADDRESS LSB 1 D3 D2 D1 D0 ACK MSB DATA DATA 1 to DATA n LSB ACK P
D96AU422
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TDA7443D
POWER ON RESET CONDITION
MSB D7 1 D6 1 D5 1 D4 1 D3 1 D2 1 D1 1 LSB D0 0
DATA BYTES Address=(HEX) 10001000 FUNCTION SELECTION: First byte (subaddress)
MSB D7 X X X X X X X D6 X X X X X X X D5 X X X X X X X D4 B B B B B B B D3 0 0 0 0 0 0 0 D2 0 0 0 0 1 1 1 D1 0 0 1 1 0 0 1 LSB D0 0 1 0 1 0 1 0 INPUT AGC SURROUND VOLUME TONE BALANCE "L" BALANCE "R" SUBADDRESS
B=1: INCREMENTAL BUS; ACTIVE B=0: NO INCREMENTAL BUS X= INDIFFERENT 0/1 INPUT
MSB D7 D6 D5 D4 D3 D2 0 0 0 0 1 0 1 0 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 D1 0 0 1 1 X LSB D0 0 1 0 1 X SUBADDRESS INPUT SELECT IN1 IN2 IN3 IN4 IN5 MUTE Output Mute OFF Output Mute ON SURROUND IN SELECT Surround ONl Mute INPUT GAIN 0dB 2dB 4dB 6dB 8dB 10dB 12dB 14dB
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TDA7443D
AGC
MSB D7 D6 D5 D4 D3 D2 D1 LSB SUBADDRESS D0 AGC MODE 0 1 OFF ON DETECTOR 0 1 OFF ON RELEASE CURRENT 0 1 OFF ON ATTACK TIME 0 0 1 1 0 1 0 1 ATTACK1 ATTACK2 ATTACK3 ATTACK4 TARGET LEVEL 0 0 1 1 0 1 0 1 TARGET1 TARGET2 TARGET3 TARGET4 ZEROCROSS 0 1 OFF ON
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TDA7443D
SURROUND
MSB D7 D6 D5 D4 D3 D2 D1 LSB SUBADDRESS D0 SURROUND MODE 0 1 PSEUDO STEREO MUSIC EFFECT CONTROL 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -6 dB -7 dB -8 dB -9 dB -10 dB -11 dB -12 dB -13 dB -14 dB -15 dB -16 dB -17 dB -18 dB -19 dB -20 dB -21 dB PHASE SHIFT RESISTOR 0 0 1 1 0 1 0 1 12 kohm 14 kohm 18 kohm 37 kohm
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TDA7443D
VOLUME
MSB D7 D6 D5 D4 D3 D2 D1 LSB SUBADDRESS D0 VOLUME IN SELECT 0 0 1 0 1 X Surround Non Surround Mute 1dB STEPS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 8dB STEPS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB
VOLUME=0 to -63dB
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TDA7443D
TREBLE & BASS
MSB D7 D6 D5 D4 D3 D2 D1 LSB SUBADDRESS D0 TREBLE 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -14 dB -12 dB -10 dB -8 dB -6 dB -4 dB -2 dB 0 dB 14 dB 12 dB 10 dB 8 dB 6 dB 4 dB 2 dB 0 dB BASS 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 -14 dB -12 dB -10 dB -8 dB -6 dB -4 dB -2 dB 0 dB 14 dB 12 dB 10 dB 8 dB 6 dB 4 dB 2 dB 0 dB
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TDA7443D
BALANCE
MSB D7 D6 D5 D4 D3 D2 D1 LSB SUBADDRESS D0 1dB STEPS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB -1dB -2dB -3dB -4dB -5dB -6dB -7dB 8dB STEPS 0 0 0 0 1 1 1 1 0 0 1 1 0 0 1 1 0 1 0 1 0 1 0 1 0dB -8dB -16dB -24dB -32dB -40dB -48dB -56dB
VOLUME=0 to -63dB
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TDA7443D
DIM. MIN. A a1 b b1 C c1 D E e e3 F L S 7.4 0.4 17.7 10 0.1 0.35 0.23
mm TYP. MAX. 2.65 0.3 0.49 0.32 0.5 45 (typ.) 18.1 10.65 1.27 16.51 7.6 1.27 0.291 0.016 0.697 0.394 0.004 0.014 0.009 MIN.
inch TYP. MAX. 0.104 0.012 0.019 0.013 0.020
OUTLINE AND MECHANICAL DATA
0.713 0.419 0.050 0.65 0.299 0.050
SO28
8 (max.)
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TDA7443D
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics 2002 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com
(R)
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